1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, relates to a design for facilitating a test of a semiconductor memory device in which input and output of a plurality of data at the same address are allowed.
2. Description of the Related Art
In recent years, semiconductor integrated circuit devices have been integrated to a higher extent, and in particular, the capacities of semiconductor memory devices have been significantly increased. This increase of the capacities, however, have caused the following disadvantages.
In an 8-bit computer, data of 8 bits can be simultaneously handled, and a unit of data stored in a memory is generally 8 bits. Such memory device may be formed, using semiconductor memories each having a capacity of 16 mega (M) bits per one chip, as shown in FIG. 1.
Referring to FIG. 1, a memory includes eight 16-Mbit semiconductor memory chips 212a-212h. One bit is stored at the same address of each of the memory chips 212a-212h, and data of 8 bits stored in the same address is handled as one byte. Thus, in a write operation, the same address in each of the memory chips 212a-212h is designated, and each bit in one byte is written in the corresponding memory chip. In a read operation, the same address in each of the memory chips 212a-212h is designated for reading one bit, whereby data of 1 byte is formed.
In the memory thus constructed, addresses up to 16 Mbits are available in each memory chip. The semiconductor memory chip, in which different addresses are allocated to the respective bits in a 16 Mbit memory region, has been referred to as "16 Mbits.times.1" (or "16.times.1") structure memory. The memory in FIG. 1 using the eight memory chips of 16.times.1 structure can store the data of 16 Mbytes.
However, such large capacity of one structure may cause a following disadvantage. If the memory capacity of a computer is insufficient, additional memories must be used. If the computer has used the memory of the structure shown in FIG. 1, eight memories each having the capacity of 16 Mbits must be added. Thus, the storage capacity of 16 Mbytes is additionally used. Eight semiconductor memory chips each having the capacity of 16 Mbits are used for this purpose.
However, it is seldom required to add such large memory at a time. The addition of the many and large memory chips at one time is expensive. For example, in personal computers, if a memory consists of semiconductor chips of large capacities, a disadvantage may be caused relating to handling of the memories.
In order to overcome the foregoing disadvantage, there has been proposed a method in which a storage capacity of one memory chip is unchanged, but a memory region of the one memory chip is divided into a plurality of memory sections (also referred to as "memory blocks"). Each memory block has addresses independent from those of the other memory blocks, and multiple data are stored at the same address in one chip.
Referring to FIG. 2, description will be made on a semiconductor memory chip in which each memory region of 16 Mbits is divided into four memory blocks each having a capacity of 4 Mbits (this structure is referred to as "4 Mbits.times.4" structure or "4.times.4" structure). A semiconductor memory chip 214a includes memory blocks 216a, 218a, 220a and 222a each having a storage capacity of 4 Mbits. Each memory block stores one bit of data at one address. This memory chip 214a stores 4 bits at the same address. Similarly, the semiconductor memory chip 214b of 4.times.4 structure includes four memory blocks 216b (not shown), 218b, 220b and 222b. The memory chip 214b can store data of 4 bits at the same address. By using the combination of the two semiconductor memory chips 214a and 214b, data of 8 bits can be stored at and read from the same address.
If two semiconductor memory chips each having the 4.times.4 structure are used, input and output of data of 1 byte is allowed. Consequently, two semiconductor memory chips each having a capacity of 16 Mbits can achieve a function similar to that of the memory shown in FIG. 1.
The semiconductor memory chip having the 4.times.4 structure shown in FIG. 2 has an advantage that the storage capacity of a minimum unit can be reduced while using the semiconductor memory chip of a large capacity. In an example shown in FIG. 2, a function similar to that of the memory in FIG. 1 is achieved, and also the storage capacity is 4 Mbytes, i.e., a quarter of that (16 Mbytes) of the memory in FIG. 1. By reducing the unit of the storage capacity of the minimum structure, the unit of the storage capacity for addition can be significantly reduced, compared with that of the structure shown in FIG. 1. This enables a specific design of configuration of the memory, and facilitates the change of configuration.
Particularly, if a main stream of computers changes from the current 16 bit computers to 32 bit computers, the unit of data handled in one time changes from 16 bits to 32 bits. If the memory of the configuration shown in FIG. 1 were used, the minimum unit of the memory would be 64 Mbytes (16 Mbits.times.32=2 Mbytes.times.32), which would be almost unnecessary for personal users. Also such memories are excessively expensive, and thus may be unavailable for the personal users in some cases. In such case, the memory chip shown in FIG. 2 can be expected to fully satisfy demand of such users.
FIG. 3 is a block diagram showing a semiconductor memory chip having a structure similar to the semiconductor memory chip 214a of the 4 Mbits.times.4 structure, and specifically, showing a 1 Mbit semiconductor memory chip 230 of a 256 kilobit (Kbit).times.4 structure.
Referring to FIG. 3, the semiconductor memory chip 230 have pins 48, 50, 52, 66 which receive an external column address strobe (CAS) signal, a row address strobe (RAS) signal, a write control (WE) signal and an output enable (OE) signal, respectively. The semiconductor memory chip 230 also has address signal input pins 32 receiving an address signal (A.sub.0 -A.sub.8) of 9 bits, a power supply pin receiving a supply voltage Vcc, a ground pin receiving a ground potential Vss, four input/output pins (DO.sub.1 -DO.sub.4) 62 for transmitting data, and a no-connection pin (NC pin) 234.
The semiconductor memory chip 230 is provided with a memory cell array 42 divided into four memory blocks 42a-42d. Each of the memory blocks 42a-42d has a storage capacity of 2.sup.3 .times.2.sup.9 =256 Kbits. Thus, the memory cell 29 array 42 has a storage capacity of 1 Mbit as a whole.
The semiconductor memory chip 230 further includes a row and column address buffer 34 connected to the address signal input pins 32, row and column decoders 36 and 38 connected to the row and column address buffer 34, and sense amplifiers 40 connected to the column decoder 38 and the memory cell array 42, as well as a data input buffer 44 and a data output buffer 46 connected between the sense amplifiers 40 and the input/output pins 62.
CAS signal pin 48 and RAS signal pin 50 are connected to a clock signal generating circuit 232. The clock signal generating circuit 232 serves to apply a clock signal for determining an operation cycle of the semiconductor memory chip 230 to the row and column address buffer 34, row decoder 36, column decoder 38, sense amplifiers 40 and data output buffer 46. An AND circuit 56 is connected to the clock signal generating circuit 232 and the WE signal pin 52. The WE signal is applied to one of the inputs of the AND circuit 56 after being inverted. The AND circuit 56 is synchronized with the clock signal applied from the clock signal generating circuit 232 to apply the signal formed by inversion of the WE signal to the data input buffer 44 and data output buffer 46. The OE signal is applied to the data output buffer 46.
The semiconductor memory chip 230 of the 256 Kbits.times.4 structure in the prior art shown in FIG. 3 operates as follows. The external row address signal is applied to the address signal input pins 32. The row and column address buffer 34 temporarily stores it and then applies the same to the row decoder 36. The row decoder 36 decodes the row address signal and selects corresponding one word line in each of the memory cell blocks 42a-42d. Then, the address signal input pins 32 receive the externally applied column address signal. The row and column address buffer 34 temporarily stores it and then applies the same to the column decoder 38. The column decoder 38 selects the corresponding bit line in each of the memory cell blocks 42a-42d by means of the sense amplifiers 40.
In the data write operation, data of 4 bits are supplied through the I/O pins 62 to the data input buffer 44. The memory blocks 42a-42d each receive the 1 bit of the data through the sense amplifiers 40. In each of the memory blocks 42a-42d, the data of 1 bit is written into the memory cell located at the crossing of the selected word line and selected bit line.
In the read operation, the memory cells are selected similarly to the foregoing write operation. In each of the memory blocks 42a-42d, 1 bit of the data is read from the memory cell located at the crossing of the selected word line and the selected bit line. The 4 bits thus read are applied through the sense amplifiers 40 to the data output buffer 46 and are temporarily stored therein. The data output buffer 46 externally supplies the data of 4 bits through the I/O pins 62 in response to the OE signal.
Whether the semiconductor memory chip 230 of the 256 Kbits.times.4 structure operates normally or not can be determined in the following manner, using a dedicated tester. First, the tester is connected to the I/O pins 62, and predetermined data is written into each of the memory blocks 42a-42d. One bit of the data written in each memory block, i.e., 4 bits in total, is read from the same address in each memory block, and each data of 4 bits thus read is applied to the tester through the I/O pins 62. The tester compares the received 4-bit signal with the original data written at the address from which the received 4 bits are read. If all the bits coincide with each other, the tester determines as normal. If there is noncoincidence of at least one bit, it determines as abnormal, in which case the semiconductor memory chip is dealt with as unacceptable.
The semiconductor memory device, which has the memory cell array divided into the multiple memory blocks as described above, has such a disadvantage that it requires many pins for the input and output of data, compared with the memory handling the whole memory cells as one address space. On the other hand, it has such an advantage that, since it allows simultaneous testing of all the memory blocks, it requires less time for testing the memory cell array, compared with the semiconductor memory chip having the memory cell array not divided into memory blocks and having an equal storage capacity. However, if the memory cell array were divided into more memory blocks in order to reduce the test time, the number of required I/O pins would also increase. This would also increase the number of pins in the tester, resulting in increase of cost of a hardware of the tester.